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VLSI & Digital Logic Design Lab

ECE LAB 3

CMOS Transistor Physics · 8-Bit ALU · Logic Synthesis · Dynamic K-Map Solver · FSM State Machines

⚡ ECE Lab 📡 Telecom & Protocols

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⚡ 1-CLICK VLSI SHARE•Logic Gates & Truth Tables Sandbox

Share this live interactive digital logic & VLSI module with classmates, students & study groups.

Input Stimulus Signals

Toggle binary inputs A and B to test real-time gate responses

AND Gate (74HC08)A · B

High only when both inputs are 1

Output (Y):0 (LOW)

OR Gate (74HC32)A + B

High when at least one input is 1

Output (Y):0 (LOW)

NOT Gate (Inverter)A'

Inverts Input A (Single input)

Output (Y):1 (HIGH)

NAND Gate (74HC00)(A · B)'

Universal Gate: Low only when both are 1

Output (Y):1 (HIGH)

NOR Gate (74HC02)(A + B)'

Universal Gate: High only when both are 0

Output (Y):1 (HIGH)

XOR Gate (74HC86)A ⊕ B

Odd Parity: High when inputs differ

Output (Y):0 (LOW)

XNOR Gate (74HC7266)(A ⊕ B)'

Equivalence: High when inputs are equal

Output (Y):1 (HIGH)

💻Hardware Description Language (HDL) Synthesis CodeIEEE 1364 Verilog & VHDL-93

// IEEE 1364-2001 Synthesizable Verilog
module logic_gates_sandbox (
    input  wire a,
    input  wire b,
    output wire out_and,
    output wire out_or,
    output wire out_xor,
    output wire out_nand,
    output wire out_nor,
    output wire out_not
);
    assign out_and  = a & b;
    assign out_or   = a | b;
    assign out_xor  = a ^ b;
    assign out_nand = ~(a & b);
    assign out_nor  = ~(a | b);
    assign out_not  = ~a;
endmodule

Input Stimulus Signals

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